

`include "defines.v"

//----------------------------------------------------------------
//Module Name : axi_arbi
//Description of module:
//deside the request 
//----------------------------------------------------------------
//Designer:	Tang Pengyu
//Date: 2021/09/13	  
//----------------------------------------------------------------

module	axi_arbi(
//if request
	input	if_valid_i,
	output	reg if_ready_o,				//->if_stage
	input	if_req_i,
	output	reg [63:0]	if_data_o,
	input	[63:0]	if_addr_i,
	input	[1:0]	if_size_i,
	output	reg [1:0]	if_resp_o,

//data request
	input	ls_valid_i,
	output	reg ls_ready_o,
	input	ls_req_i,
	output	reg [63:0]	load_data_o,
	input	[63:0]	ls_addr_i,			//exe_data
//	input	[1:0]	store_data_i,		//op2
	input	[1:0]	ls_size_i,
	output	reg [1:0]	ls_resp_o,
	
//to axi_rw
	output	reg rw_valid_o,
	input	rw_ready_i,
	output	reg rw_req_o,
	input	[63:0]	data_read_i,
//	output	[63:0]	data_write_o,		//op2
	output	reg [63:0]	rw_addr_o,
	output	reg [1:0]	rw_size_o,
	input	[1:0]	rw_resp_i
	);
wire	[1:0]	ls_if_valid;
assign	ls_if_valid = {ls_valid_i,if_valid_i};
	
always @(*)	begin
	case(ls_if_valid)
		2'b10,2'b11:	begin			//ls_valid,all valid
			rw_valid_o = ls_valid_i;
			rw_req_o = ls_req_i;
			rw_addr_o = ls_addr_i;
			rw_size_o = ls_size_i;
			
			ls_resp_o = rw_resp_i;
			load_data_o = data_read_i;
			ls_ready_o = rw_ready_i;
			
			if_resp_o = 2'b00;
			if_data_o = 64'd0;
			if_ready_o = 1'b0;	
		end
		
		2'b01:	begin			//if valid
			rw_valid_o = if_valid_i;
			rw_req_o = if_req_i;
			rw_addr_o = if_addr_i;
			rw_size_o = if_size_i;
			
			ls_resp_o = 2'b00;
			load_data_o = 64'd0;
			ls_ready_o = 1'b0;
			
			if_resp_o = rw_resp_i;
			if_data_o = data_read_i;
			if_ready_o = rw_ready_i;
			
		end
		
		2'b00:	begin			//all no valid
			rw_valid_o = 1'b0;
			rw_req_o = 1'b0;
			rw_addr_o = 64'd0;
			rw_size_o = 2'b00;
			
			ls_resp_o = 2'b00;
			load_data_o = 64'd0;
			ls_ready_o = 1'b0;
			
			if_resp_o = 2'b00;
			if_data_o = 64'd0;
			if_ready_o = 1'b0;
		
		end


	endcase
end


endmodule
